LM3S1G21 Datasheet, PDF (500/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

External Peripheral Interface (EPI)
Bit/Field
30
29
28
27
26
Name
CLKGATE
reserved
RDYEN
FRMPIN
FRM50
Type
R/W
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
Description
Clock Gated
Value Description
0 The EPI clock is free running.
1 The EPI clock is output only when there is data to write or read
(current transaction); otherwise the EPI clock is held low.
Note that EPI0S27 is an iRDY signal if RDYEN is set. CLKGATE is ignored
if CLKPIN is 0 or if the COUNT0 field in the EPIBAUD register is cleared.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Ready Enable
Value Description
0 The external peripheral does not drive an iRDY signal and is
assumed to be ready always.
1 The external peripheral drives an iRDY signal into pin EPI0S27.
The ready enable signal may only be used with a free-running EPI clock
(CLKGATE=0).
The external iRDY signal is sampled on the falling edge of the EPI clock.
Setup and hold times must be met to ensure registration on the next
falling EPI clock edge.
This bit is ignored if CLKPIN is 0 or CLKGATE is 1.
Framing Pin
Value Description
0 No framing signal is output.
1 A framing signal is output on EPI0S30.
Framing has no impact on data itself, but forms a context for the external
peripheral. When used with a free-running EPI clock, the FRAME signal
forms the valid signal. When used with a gated EPI clock, it is usually
used to form a frame size.
50/50 Frame
Value Description
0 The FRAME signal is output as a single pulse, and then held
low for the count.
1 The FRAME signal is output as 50/50 duty cycle using count
(see FRMCNT).
This bit is ignored if FRMPIN is 0.
500
January 22, 2012
Texas Instruments-Production Data