LM3S1G21 Datasheet, PDF (28/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Revision History
Revision History
The revision history table notes changes made between the indicated revisions of the LM3S1G21
data sheet.
Table 1. Revision History
Date
January 2012
Revision Description
11425 ■ In System Control chapter:
– Clarified that an external LDO cannot be used.
– Clarified system clock requirements when the ADC module is in operation.
– Added important note to write the RCC register before the RCC2 register.
■ In Hibernation chapter:
– Changed terminology from non-volatile memory to battery-backed memory.
– Numerous clarifications, including adding a section "System Implementation".
– Clarified Hibernation module register reset conditions.
■ In Internal Memory chapter, clarified programming and use of the non-volatile registers.
■ In GPIO chapter, corrected "GPIO Pins With Non-Zero Reset Values" table and added note that if
the same signal is assigned to two different GPIO port pins, the signal is assigned to the port with
the lowest letter.
■ In EPI chapter:
– Clarified table "Capabilities of Host Bus 8 and Host Bus 16 Modes".
– Corrected bit and register resets for FREQ (Frequency Range) in EPI SDRAM Configuration
(EPISDRAMCFG) register.
– Corrected bit and register resets for MAXWAIT (Maximum Wait) in EPI Host-Bus 8 Configuration
(EPIHB8CFG) and EPI Host-Bus 16 Configuration (EPIHB16CFG) registers. Also clarified
bit descriptions in these registers.
– Corrected bit definitions for the EPSZ and ERSZ bits in the EPI Address Map (EPIADDRMAP)
register.
– Corrected size of COUNT bit field in EPI Read FIFO Count (EPIRFIFOCNT) register.
■ In Timer chapter, clarified timer modes and interrupts.
■ In ADC chapter, added "ADC Input Equivalency Diagram".
■ In UART chapter, clarified interrupt behavior.
■ In SSI chapter, corrected SSIClk in the figure "Synchronous Serial Frame Format (Single Transfer)"
and clarified behavior of transmit bits in interrupt registers.
■ In I²C chapter, corrected bit and register reset values for IDLE bit in I²C Master Control/Status
(I2CMCS) register.
■ In Analog Comparators chapter, clarified internal reference programming.
■ In Signal Tables chapter, clarified VDDC and LDO pin descriptions.
■ In Electrical Characteristics chapter:
28
January 22, 2012
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