LM3S1G21 Datasheet, PDF (21/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Stellaris^® LM3S1G21 Microcontroller
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Register 32:
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 318
Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 319
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 321
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 322
User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 323
User Register 3 (USER_REG3), offset 0x1EC ................................................................. 324
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 325
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 326
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 327
Flash Memory Protection Read Enable 4 (FMPRE4), offset 0x210 .................................... 328
Flash Memory Protection Read Enable 5 (FMPRE5), offset 0x214 .................................... 329
Flash Memory Protection Read Enable 6 (FMPRE6), offset 0x218 .................................... 330
Flash Memory Protection Read Enable 7 (FMPRE7), offset 0x21C ................................... 331
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 332
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 333
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 334
Flash Memory Protection Program Enable 4 (FMPPE4), offset 0x410 ............................... 335
Flash Memory Protection Program Enable 5 (FMPPE5), offset 0x414 ............................... 336
Flash Memory Protection Program Enable 6 (FMPPE6), offset 0x418 ............................... 337
Flash Memory Protection Program Enable 7 (FMPPE7), offset 0x41C ............................... 338
Micro Direct Memory Access (μDMA) ........................................................................................ 339
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 363
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 364
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 365
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 370
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 372
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 373
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 374
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 375
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 376
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 377
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 378
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 379
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 380
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 381
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 382
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 383
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 384
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 385
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 386
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 387
Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 388
Register 22: DMA Channel Interrupt Status (DMACHIS), offset 0x504 .................................................. 389
Register 23: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 390
Register 24: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 391
Register 25: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 392
Register 26: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 393
Register 27: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 394
January 22, 2012
21
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