LM3S1G21 Datasheet, PDF (26/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Table of Contents
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 735
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 736
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 737
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 738
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 739
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 740
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 741
Synchronous Serial Interface (SSI) ............................................................................................ 742
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 757
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 759
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 761
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 762
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 764
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 765
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 766
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 768
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 770
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 771
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 772
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 773
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 774
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 775
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 776
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 777
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 778
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 779
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 780
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 781
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 782
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 783
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 784
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 801
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 802
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 807
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 808
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 809
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 810
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 811
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 812
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 813
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 814
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 815
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 817
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 818
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 819
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 820
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 821
26
January 22, 2012
Texas Instruments-Production Data