LM3S1G21 Datasheet, PDF (3/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Stellaris^® LM3S1G21 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 28
About This Document .................................................................................................................... 31
Audience .............................................................................................................................................. 31
About This Manual ................................................................................................................................ 31
Related Documents ............................................................................................................................... 31
Documentation Conventions .................................................................................................................. 32
1
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.4
Architectural Overview .......................................................................................... 34
Overview ...................................................................................................................... 34
Target Applications ........................................................................................................ 36
Features ....................................................................................................................... 36
ARM Cortex-M3 Processor Core .................................................................................... 36
On-Chip Memory ........................................................................................................... 38
External Peripheral Interface ......................................................................................... 39
Serial Communications Peripherals ................................................................................ 41
System Integration ........................................................................................................ 44
Analog .......................................................................................................................... 49
JTAG and ARM Serial Wire Debug ................................................................................ 51
Packaging and Temperature .......................................................................................... 51
Hardware Details .......................................................................................................... 52
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
2.5.3
The Cortex-M3 Processor ...................................................................................... 53
Block Diagram .............................................................................................................. 54
Overview ...................................................................................................................... 55
System-Level Interface .................................................................................................. 55
Integrated Configurable Debug ...................................................................................... 55
Trace Port Interface Unit (TPIU) ..................................................................................... 56
Cortex-M3 System Component Details ........................................................................... 56
Programming Model ...................................................................................................... 57
Processor Mode and Privilege Levels for Software Execution ........................................... 57
Stacks .......................................................................................................................... 57
Register Map ................................................................................................................ 58
Register Descriptions .................................................................................................... 59
Exceptions and Interrupts .............................................................................................. 72
Data Types ................................................................................................................... 72
Memory Model .............................................................................................................. 72
Memory Regions, Types and Attributes ........................................................................... 74
Memory System Ordering of Memory Accesses .............................................................. 74
Behavior of Memory Accesses ....................................................................................... 75
Software Ordering of Memory Accesses ......................................................................... 75
Bit-Banding ................................................................................................................... 77
Data Storage ................................................................................................................ 79
Synchronization Primitives ............................................................................................. 79
Exception Model ........................................................................................................... 80
Exception States ........................................................................................................... 81
Exception Types ............................................................................................................ 81
Exception Handlers ....................................................................................................... 84
January 22, 2012
3
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