LM3S1G21 Datasheet, PDF (475/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Stellaris^® LM3S1G21 Microcontroller
Figure 10-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
BSEL0n/
BSEL1n^a
Address
Data
a _{BSEL0n and BSEL1n are available in Host-Bus 16 mode only.}
Data
Figure 10-8 on page 475 shows a write cycle with the address and data signals multiplexed (MODE
field is 0x0 in the EPIHBnCFG register). A read cycle would look similar, with the RDn strobe being
asserted along with CSn and data being latched on the rising edge of RDn.
Figure 10-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH = 0, RDHIGH
=0
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
BSEL0n/
BSEL1n^a
Address
(high order, non muxed)
Muxed
Address/Data
Address
Data
a _{BSEL0n and BSEL1n are available in Host-Bus 16 mode only.}
When using ALE with dual CSn configuration (CSCFG field is 0x3 in the EPIHBnCFG2 register), the
appropriate CSn signal is asserted at the same time as ALE, as shown in Figure 10-9 on page 476.
January 22, 2012
475
Texas Instruments-Production Data