LM3S1G21 Datasheet, PDF (488/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

External Peripheral Interface (EPI)
Register 2: EPI Main Baud Rate (EPIBAUD), offset 0x004
The system clock is used internally to the EPI Controller. The baud rate counter can be used to
divide the system clock down to control the speed on the external interface. If the mode selected
emits an external EPI clock, this register defines the EPI clock emitted. If the mode selected does
not use an EPI clock, this register controls the speed of changes on the external interface. Care
must be taken to program this register properly so that the speed of the external bus corresponds
to the speed of the external peripheral and puts acceptable current load on the pins. COUNT0 is the
bit field used in all modes except in HB8 and HB16 modes with dual chip selects when different
baud rates are selected, see page 504 and page 507. If different baud rates are used, COUNT0 is
associated with the address range specified by CS0n and COUNT1 is associated with the address
range specified by CS1.
The COUNTn field is not a straight divider or count. The EPI Clock on EPI0S31 is related to the
COUNTn field and the system clock as follows:
If COUNTn = 0,
EPIClockFreq = SystemClockFreq
otherwise:
EPIClockFreq = ^{SystemClockFreq}
⎜⎛
⎝
⎢^COUNTn⎥
⎢⎣ ₂ ⎥⎦
+
1⎟⎞
⎠
×
2
where the symbol around COUNTn/2 is the floor operator, meaning the largest integer less than or
equal to COUNTn/2.
So, for example, a COUNTn of 0x0001 results in a clock rate of ½(system clock); a COUNTn of 0x0002
or 0x0003 results in a clock rate of ¼(system clock).
EPI Main Baud Rate (EPIBAUD)
Base 0x400D.0000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
COUNT1
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COUNT0
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:16
Name
COUNT1
Type
RO
Reset
0x0000
Description
Baud Rate Counter 1
This bit field is only valid with multiple chip selects which are enabled
when the CSCFG field is 0x2 or 0x3 and the CSBAUD bit is set in the
EPIHBnCFG2 register.
This bit field contains a counter used to divide the system clock by the
count.
A count of 0 means the system clock is used as is.
488
January 22, 2012
Texas Instruments-Production Data