LM3S1G21 Datasheet, PDF (538/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

General-Purpose Timers
11.3.2.3
Input Edge-Count Mode
Note:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
In Edge-Count mode, the timer is configured as a 24-bit down-counter including the optional prescaler
with the upper count value stored in the GPTM Timer n Prescale (GPTMTnPR) register and the
lower bits in the GPTMTnR register. In this mode, the timer is capable of capturing three types of
events: rising edge, falling edge, or both. To place the timer in Edge-Count mode, the TnCMR bit of
the GPTMTnMR register must be cleared. The type of edge that the timer counts is determined by
the TnEVENT fields of the GPTMCTL register. During initialization, the GPTMTnMATCHR and
GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR
and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the
number of edge events that must be counted. Table 11-8 on page 538 shows the values that are
loaded into the timer registers when the timer is enabled.
Table 11-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode
Register
TnR
TnV
Count Down Mode
GPTMTnILR
GPTMTnILR
Count Up Mode
Not available
Not available
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event
count matches GPTMTnMATCHR and GPTMTnPMR. When the counts match, the GPTM asserts
the CnMRIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until it is cleared
by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode match interrupt is
enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnMMIS bit in
the GPTM Masked Interrupt Status (GPTMMIS) register. In this mode, the GPTMTnR register
holds the count of the input events while the GPTMTnV register holds the free-running timer value.
In addition to generating interrupts, an ADC and/or a μDMA trigger can be generated. The ADC
trigger is enabled by setting the TnOTE bit in GPTMCTL.The μDMA trigger is enabled by configuring
and enabling the appropriate μDMA channel. See “Channel Configuration” on page 343.
After the match value is reached, the counter is then reloaded using the value in GPTMTnILR and
GPTMTnPR registers, and stopped because the GPTM automatically clears the TnEN bit in the
GPTMCTL register. Once the event count has been reached, all further events are ignored until
TnEN is re-enabled by software.
Figure 11-3 on page 539 shows how Input Edge-Count mode works. In this case, the timer start
value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so
that four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted because the timer automatically clears the TnEN bit
after the current count matches the value in the GPTMTnMATCHR register.
538
January 22, 2012
Texas Instruments-Production Data