LM3S1G21 Datasheet, PDF (501/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Stellaris^® LM3S1G21 Microcontroller
Bit/Field
25:22
21
20
19
18
Name
FRMCNT
RW
reserved
WR2CYC
RD2CYC
Type
R/W
R/W
RO
R/W
R/W
Reset
0x0
0
0
0
0
Description
Frame Count
This field specifies the size of the frame in EPI clocks. The frame counter
is used to determine the frame size. The count is FRMCNT+1. So, a
FRMCNT of 0 forms a pure transaction valid signal (held high during
transactions, low otherwise).
A FRMCNT of 0 with FRM50 set inverts the FRAME signal on each
transaction. A FRMCNT of 1 means the FRAME signal is inverted every
other transaction; a value of 15 means every sixteenth transaction.
If FRM50 is set, the frame is held high for FRMCNT+1 transactions, then
held low for that many transactions, and so on.
If FRM50 is clear, the frame is pulsed high for one EPI clock and then
low for FRMCNT EPI clocks.
This field is ignored if FRMPIN is 0.
Read and Write
Value Description
0 RD and WR strobes are not output.
1 RD and WR strobes are asserted on EPI0S29 and EPI0S28.
RD is asserted high on the rising edge of the EPI clock when a
read is being performed. WR is asserted high on the rising edge
of the EPI clock when a write is being performed
This bit is forced to 1 when RD2CYC and/or WR2CYC is 1.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2-Cycle Writes
Value Description
0 Data is output on the same EPI clock cycle as the address.
1 Writes are two EPI clock cycles long, with address on one EPI
clock cycle (with the WR strobe asserted) and data written on
the following EPI clock cycle (with WR strobe de-asserted). The
next address (if any) is in the cycle following.
When this bit is set, then the RW bit is forced to be set.
2-Cycle Reads
Value Description
0 Data is captured on the EPI clock cycle with READ strobe
asserted.
1 Reads are two EPI clock cycles, with address on one EPI clock
cycle (with the RD strobe asserted) and data captured on the
following EPI clock cycle (with the RD strobe de-asserted). The
next address (if any) is in the cycle following.
When this bit is set, then the RW bit is forced to be set.
Caution – This bit must be set at all times in General-Purpose mode to
ensure proper operation.
January 22, 2012
501
Texas Instruments-Production Data