LM3S1G21 Datasheet, PDF (5/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Stellaris^® LM3S1G21 Microcontroller
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Hibernation Module .............................................................................................. 267
6.1 Block Diagram ............................................................................................................ 268
6.2 Signal Description ....................................................................................................... 268
6.3 Functional Description ................................................................................................. 269
6.3.1 Register Access Timing ............................................................................................... 269
6.3.2 Hibernation Clock Source ............................................................................................ 270
6.3.3 System Implementation ............................................................................................... 271
6.3.4 Battery Management ................................................................................................... 272
6.3.5 Real-Time Clock .......................................................................................................... 272
6.3.6 Battery-Backed Memory .............................................................................................. 273
6.3.7 Power Control Using HIB ............................................................................................. 273
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 273
6.3.9 Initiating Hibernate ...................................................................................................... 273
6.3.10 Waking from Hibernate ................................................................................................ 273
6.3.11 Interrupts and Status ................................................................................................... 274
6.4 Initialization and Configuration ..................................................................................... 274
6.4.1 Initialization ................................................................................................................. 274
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 275
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 275
6.4.4 External Wake-Up from Hibernation .............................................................................. 276
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 276
6.5 Register Map .............................................................................................................. 276
6.6 Register Descriptions .................................................................................................. 277
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7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 294
Block Diagram ............................................................................................................ 294
Functional Description ................................................................................................. 294
SRAM ........................................................................................................................ 295
ROM .......................................................................................................................... 295
Flash Memory ............................................................................................................. 297
Register Map .............................................................................................................. 302
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 303
Memory Register Descriptions (System Control Offset) .................................................. 315
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Micro Direct Memory Access (μDMA) ................................................................ 339
8.1 Block Diagram ............................................................................................................ 340
8.2 Functional Description ................................................................................................. 340
8.2.1 Channel Assignments .................................................................................................. 341
8.2.2 Priority ........................................................................................................................ 342
8.2.3 Arbitration Size ............................................................................................................ 342
8.2.4 Request Types ............................................................................................................ 342
8.2.5 Channel Configuration ................................................................................................. 343
8.2.6 Transfer Modes ........................................................................................................... 345
8.2.7 Transfer Size and Increment ........................................................................................ 353
8.2.8 Peripheral Interface ..................................................................................................... 353
8.2.9 Software Request ........................................................................................................ 353
8.2.10 Interrupts and Errors .................................................................................................... 354
8.3 Initialization and Configuration ..................................................................................... 354
8.3.1 Module Initialization ..................................................................................................... 354
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 355
January 22, 2012
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