LM3S1G21 Datasheet, PDF (11/955 Pages) Texas Instruments – Stellaris® LM3S1G21 Microcontroller

Stellaris^® LM3S1G21 Microcontroller
Figure 10-11. Write Followed by Read to External FIFO ............................................................ 477
Figure 10-12. Two-Entry FIFO ................................................................................................. 477
Figure 10-13. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 481
Figure 10-14. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,
WRCYC=1 ........................................................................................................ 481
Figure 10-15. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 482
Figure 10-16. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 482
Figure 10-17. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 482
Figure 10-18. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 483
Figure 10-19. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 483
Figure 10-20. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 483
Figure 10-21. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 483
Figure 10-22. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 484
Figure 10-23. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 485
Figure 10-24. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 485
Figure 11-1. GPTM Module Block Diagram ............................................................................ 531
Figure 11-2. Timer Daisy Chain ............................................................................................. 537
Figure 11-3. Input Edge-Count Mode Example ....................................................................... 539
Figure 11-4. 16-Bit Input Edge-Time Mode Example ............................................................... 540
Figure 11-5. 16-Bit PWM Mode Example ................................................................................ 541
Figure 12-1. WDT Module Block Diagram .............................................................................. 578
Figure 13-1. ADC Module Block Diagram ............................................................................... 603
Figure 13-2. ADC Sample Phases ......................................................................................... 607
Figure 13-3. Sample Averaging Example ............................................................................... 608
Figure 13-4. ADC Input Equivalency Diagram ......................................................................... 609
Figure 13-5. Internal Voltage Conversion Result ..................................................................... 610
Figure 13-6. External Voltage Conversion Result with 3.0-V Setting ......................................... 611
Figure 13-7. External Voltage Conversion Result with 1.0-V Setting ......................................... 611
Figure 13-8. Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 613
Figure 13-9. Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 613
Figure 13-10. Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 614
Figure 13-11. Internal Temperature Sensor Characteristic ......................................................... 615
Figure 13-12. Low-Band Operation (CIC=0x0) .......................................................................... 617
Figure 13-13. Mid-Band Operation (CIC=0x1) .......................................................................... 618
Figure 13-14. High-Band Operation (CIC=0x3) ......................................................................... 619
Figure 14-1. UART Module Block Diagram ............................................................................. 679
Figure 14-2. UART Character Frame ..................................................................................... 682
Figure 14-3. IrDA Data Modulation ......................................................................................... 684
Figure 14-4. LIN Message ..................................................................................................... 686
Figure 14-5. LIN Synchronization Field ................................................................................... 687
Figure 15-1. SSI Module Block Diagram ................................................................................. 743
Figure 15-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 747
Figure 15-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 747
Figure 15-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 748
Figure 15-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 748
Figure 15-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 749
Figure 15-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 750
Figure 15-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 750
January 22, 2012
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Texas Instruments-Production Data