DS90UH947-Q1 Datasheet, PDF (75/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

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DS90UH947-Q1
SNLS455 – NOVEMBER 2014
9.2.2 Detailed Design Procedure
9.2.2.1 High Speed Interconnect Guidelines
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas
Instruments web site at: LVDS Owner's Manual.
9.2.3 Application Curves
9.2.3.1 Application Performance Plots
Figure 40 corresponds to 1080p60 video application with 2-lane FPD-Link III output. Figure 41 corresponds to
3.36Gbps single-lane output from 96MHz input OpenLDI clock.
Figure 40. 1080p60 Video at 2.6 Gbps Serial Line Rate
(One of Two Lanes)
Figure 41. Serializer Output at 3.36Gbps (96MHz OpenLDI
Clock)
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