DS90UH947-Q1 Datasheet, PDF (47/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

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ADD
(dec)
23
ADD
(hex)
0x17
Register Name
I2C Control
24
0x18 SCL High Time
25
0x19 SCL Low Time
26
0x1A Data Path Control 2
Copyright © 2014, Texas Instruments Incorporated
DS90UH947-Q1
SNLS455 – NOVEMBER 2014
Table 10. Serial Control Bus Registers (continued)
Bit(s)
7
6:4
3:0
7:0
7:0
7
6:2
1
0
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
(hex)
0x1E
0xA1
0xA5
0x00
0x00
Function
Description
I2C Pass All
0: Enable Forward Control Channel pass-through only of I2C
accesses to I2C Slave IDs matching either the remote Deserializer
Slave ID or the remote Slave ID (default).
1: Enable Forward Control Channel pass-through of all I2C accesses
to I2C Slave IDs that do not match the Serializer I2C Slave ID.
SDA Hold Time
Internal SDA hold time:
Configures the amount of internal hold time provided for the SDA input
relative to the SCL input. Units are 40 nanoseconds.
I2C Filter Depth Configures the maximum width of glitch pulses on the SCL and SDA
inputs that will be rejected. Units are 5 nanoseconds.
SCL HIGH Time
I2C Master SCL High Time:
This field configures the high pulse width of the SCL output when the
Serializer is the Master on the local I2C bus. Units are 40 ns for the
nominal oscillator clock frequency. The default value is set to provide
a minimum 5us SCL high time with the internal oscillator clock running
at 26.25MHz rather than the nominal 25MHz. Delay includes 5
additional oscillator clock periods.
Min_delay = 38.0952ns * (TX_SCL_HIGH + 5).
SCL LOW Time
I2C SCL Low Time:
This field configures the low pulse width of the SCL output when the
Serializer is the Master on the local I2C bus. This value is also used
as the SDA setup time by the I2C Slave for providing data prior to
releasing SCL during accesses over the Bidirectional Control Channel.
Units are 40 ns for the nominal oscillator clock frequency. The default
value is set to provide a minimum 5us SCL low time with the internal
oscillator clock running at 26.25MHz rather than the nominal 25MHz.
Delay includes 5 additional clock periods.
Min_delay = 38.0952ns * (TX_SCL_LOW + 5).
BLOCK_REPEA
TER_I2S_MODE
Block automatic I2S mode configuration in repeater.
0: I2S mode (2-channel, 4-channel, or surround) is detected from the
in-band audio signaling in a repeater.
1: Disable automatic detection of I2S mode.
Reserved.
MODE_28B
Enable 28-bit Serializer Mode.
0: 24-bit high-speed data + 3 low-speed control (DE, HS, VS).
1: 28-bit high-speed data mode.
I2S Surround
Enable 5.1- or 7.1-channel I2S audio transport:
0: 2-channel or 4-channel I2S audio is enabled as configured in
register 0x12 bits 3 and 0 (default).
1: 5.1- or 7.1-channel audio is enabled.
Note that I2S Data Island Transport is the only option for surround
audio. Also note that in a repeater, this bit may be overridden by the
in-band I2S mode detection.
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