DS90UH947-Q1 Datasheet, PDF (64/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

DS90UH947-Q1
SNLS455 – NOVEMBER 2014
ADD
(dec)
192
ADD
(hex)
0xC0
Register Name
HDCP_DBG
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Table 10. Serial Control Bus Registers (continued)
Bit(s)
7
6
5
4
3
2
1
0
Register
Type
RW
RW
RW
RW
RW
RW
Default
(hex)
0x00
Function
Description
Reserved.
HDCP_I2C_TO_
DIS
HDCP I2C Timeout Disable: Setting this bit to a 1 will disable the bus
timeout function in the HDCP I2C master. When enabled, the bus
timeout function allows the I2C master to assume the bus is free if no
signaling occurs for more than 1 second.
Reserved.
DIS_RI_SYNC
Disable Ri Synchronization check: Ri is normally checked both before
and after the start of frame 128. The check at frame 127 ensures
synchronization between the two. Setting this bit to a 1 will disable the
check at frame 127.
RGB_CHKSUM_ Enable RBG video line checksum: Enables sending of ones-
EN
complement checksum for each 8-bit RBG data channel following end
of each video data line.
FC_TESTMODE
Frame Counter Testmode: Speeds up frame counter used for Pj and
Ri verification. When set to a 1, Pj is computed every 2 frames and Ri
is computed every 16 frames. When set to a 0, Pj is computed every
16 frames and Ri is computed every 128 frames.
TMR_SPEEDUP Timer Speedup: Speed up HDCP authentication timers.
HDCP_I2C_FAS
T
HDCP I2C Fast Mode Enable:
Setting this bit to a 1 will enable the HDCP I2C Master in the HDCP
Receiver to operation with Fast mode timing. If set to a 0, the I2C
Master will operation with Standard mode timing. This bit is mirrored in
the IND_STS register.
64
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