DS90UH947-Q1 Datasheet, PDF (69/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

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ADD
(dec)
200
ADD
(hex)
0xC8
Register Name
NVM_CTL
206
0xCE BLUE_SCREEN
208
0xD0 IND_STS
Copyright © 2014, Texas Instruments Incorporated
DS90UH947-Q1
SNLS455 – NOVEMBER 2014
Table 10. Serial Control Bus Registers (continued)
Bit(s)
7
6
5
4:3
2
1
0
7:0
7
6
5
4
3:2
1
0
Register
Type
R
R
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
R
R
Default
(hex)
0x00
0x00
0xFF
0x00
0x00
Function
Description
NVM_PASS
NVM Verify pass: This bit indicates the completion status of the NVM
verification process. This bit is valid only when NVM_DONE is
asserted.
0: NVM Verify failed.
1: NVM Verify passed.
NVM_DONE
NVM Verify done: This bit indicates that the NVM Verifcation has
completed.
Reserved.
Reserved.
NVM_VFY
NVM Verify: Setting this bit will enable a verification of the NVM con-
tents. This is done by reading all NVM keys, computing a SHA-1 hash
value, and verifying against the SHA-1 hash stored in NVM. This bit
will be cleared upon com-pletion of the NVM Verification.
Reserved.
Reserved.
BLUE_SCREEN Blue Screen Data Value: Provides the 8-bit data value sent on the
_VAL
Blue channel when the HDCP Transmitter is sending a blue screen.
IA_RST
Indirect Access Reset: Setting this bit to a 1 will reset the I2C Master
in the HDCP Receiver. As this may leave the I2C bus in an
indeterminate state, it should only be done if the Indirect Access
mechanism is not able to complete due to an error on the destination
I2C bus.
I2C_TO_SPEED I2C Timer Speedup: For diagnostic purposes allow speedup of of the
1 second idle timer to 50us. Texas Instruments use only, should be
marked as Reserved in datasheet.
I2C_TO_DIS
I2C Timeout Disable: Setting this bit to a 1 will disable the bus timeout
function in the I2C master. When enabled, the bus timeout function
allows the I2C master to assume the bus is free if no signaling occurs
for more than 1 second.
I2C_FAST
I2C Fast mode Enable: Setting this bit to a 1 will enable the I2C
Master in the HDCP Receiver to operation with Fast mode timing. If
set to a 0, the I2C Master will operation with Standard mode timing.
Reserved.
IA_ACK
Indirect Access Acknowledge: The acknowledge bit indicates that a
valid acknowledge was received upon completion of the I2C read or
write to the slave. A value of 0 indicates the read/write did not
complete successfully.
IA_DONE
Indirect Access Done: Set to a 1 to indicate completion of Indirect
Register Access. This bit will be cleared or read or by start of a new
Indirect Register Access.
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