DS90UH947-Q1 Datasheet, PDF (15/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

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DS90UH947-Q1
SNLS455 – NOVEMBER 2014
Feature Description (continued)
The device supports OpenLDI clocks in the range of 25 MHz to 96 MHz over one lane, or 50MHz to 170MHz
over two lanes. The FPD-Link III serial stream rate is 3.36 Gbps maximum (875 Mbps minimum) , or 2.975 Gbps
maximum per lane (875 Mbps minimum) when transmitting over both lanes.
8.3.2 Back Channel Data Transfer
The Backward Channel provides bidirectional communication between the display and host processor. The
information is carried from the deserializer to the serializer as serial frames. The back channel control data is
transferred over both serial links along with the high-speed forward data, DC balance coding and embedded
clock information. This architecture provides a backward path across the serial link together with a high speed
forward channel. The back channel contains the I2C, CRC and 4 bits of standard GPIO information with 5, 10, or
20 Mbps line rate (configured by the compatible deserializer).
8.3.3 FPD-Link III Port Register Access
Since the DS90UH947-Q1 contains two downstream ports, some registers need to be duplicated to allow control
and monitoring of the two ports. To facilitate this, a TX_PORT_SEL register controls access to the two sets of
registers. Registers that are shared between ports (not duplicated) will be available independent of the settings in
the TX_PORT_SEL register.
Setting the TX_PORT0_SEL or TX_PORT1_SEL bit will allow a read of the register for the selected port. If both
bits are set, port1 registers will be returned. Writes will occur to ports for which the select bit is set, allowing
simultaneous writes to both ports if both select bits are set.
Setting the PORT1_I2C_EN bit will enable a second I2C slave address, allowing access to the second port
registers through the second I2C address. If this bit is set, the TX_PORT0_SEL and TX_PORT1_SEL bits will be
ignored.
8.3.4 OpenLDI Input Frame And Color Bit Mapping Select
The DS90UH947-Q1 can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes,
shown in Figure 13 and Figure 14. Each frame corresponds to a single pixel clock (PCLK) cycle. The LVDS clock
input to CLK± follows a 4:3 duty cycle scheme, with each 28-bit pixel frame starting with two LVDS bit clock
periods high, three low, and ending with two high. The mapping scheme is controlled by MAPSEL strap option or
by Register (Table 10).
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