DS90UH947-Q1 Datasheet, PDF (53/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

www.ti.com
ADD
(dec)
87
ADD
(hex)
0x57
Register Name
TDM_CONFIG
DS90UH947-Q1
SNLS455 – NOVEMBER 2014
Table 10. Serial Control Bus Registers (continued)
Bit(s)
7:4
3
2
1:0
Register
Type
RW
RW
RW
Default
(hex)
0x00
0x00
0x02
Function
Description
Reserved.
TDM_FS_MODE
TDM Frame Sync Mode: Sets active level for the Frame Sync for the
TDM audio. The Frame Sync signal provides an active pulse to
indicate the first sample data on the TDM data signal.
0 : Active high Frame Sync.
1 : Active low Frame Sync (similar to I2S word select).
This bit is used for both the output of the I2S to TDM conversion and
the input of the TDM to I2S conversion.
TDM_DELAY
TDM Data Delay: Controls data delay for TDM audio samples from the
active Frame Sync edge.
0 : Data is not delayed from Frame Sync (data is left justified).
1 : Data is delayed 1 bit from Frame Sync.
This bit is used for both the output of the I2S to TDM conversion and
the input of the TDM to I2S conversion.
TDM_FS_WIDT
H
TDM Frame Sync Width: Indicates width of TDM Frame Sync pulse for
I2S to TDM conversion.
00 : FS is 50/50 duty cycle.
01 : FS is one slot/channel wide.
1x : FS is 1 clock pulse wide.
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: DS90UH947-Q1
Submit Documentation Feedback
53