DS90UH947-Q1 Datasheet, PDF (14/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

DS90UH947-Q1
SNLS455 – NOVEMBER 2014
8 Detailed Description
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8.1 Overview
The DS90UH947-Q1 converts a single or dual FPD-Link (Open LDI) interface (up to 8 LVDS lanes + 1 clock) to
an FPD-Link III interface. This device transmits a 35-bit symbol over a single serial pair operating up to 3.36Gbps
line rate, or two serial pairs operating up to 2.975Gbps line rate. The serial stream contains an embedded clock,
video control signals, RGB video data, and audio data. The payload is DC-balanced to enhance signal quality
and support AC coupling.
The DS90UH947-Q1 serializer is intended for use with a DS90UH926Q-Q1, DS90UH928Q-Q1, DS90UH940-Q1,
DS90UH948-Q1 deserializer.
The DS90UH947-Q1 serializer and companion deserializer incorporate an I2C compatible interface. The I2C
compatible interface allows programming of serializer or deserializer devices from a local host controller. In
addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between
serializer/deserializer as well as remote I2C slave devices.
The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward
channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to
serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial
link from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at
either side of the serial link.
8.2 Functional Block Diagram
Open-LDI
Open-LDI
Open LDI
Analog
Single/Dual
Control
OLDI
Interface
PAT
GEN
HDCP
FPD3
Output
Select
Audio
Config
Regs
Clocks
DFT
FPD-Link III TX
Digital
FPD-Link III TX
Digital
I2C
Interface
FPD3 TX
Analog
FPD3 TX
Analog
FPD-Link III
FPD-Link III
I2S
I2C
8.3 Feature Description
8.3.1 High Speed Forward Channel Data Transfer
The High Speed Forward Channel is composed of 35 bits of data containing RGB data, sync signals, I2C,
GPIOs, and I2S audio transmitted from serializer to deserializer. Figure 12 illustrates the serial stream per clock
cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized,
balanced and scrambled.
C1
C0
Figure 12. FPD-Link III Serial Stream
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