DS90UH947-Q1 Datasheet, PDF (19/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

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DS90UH947-Q1
SNLS455 – NOVEMBER 2014
Feature Description (continued)
3. ”+” to GND short
4. ”-” to GND short
5. ”+” to battery short
6. ”-” to battery short
7. Cable is linked incorrectly (DOUT+/DOUT- connections reversed)
Note: The device will detect any of the above conditions, but does not report specifically which one has occurred.
8.3.8 Interrupt Pin (INTB)
The INTB pin is an active low interrupt output pin that acts as an interrupt for various local and remote interrupt
conditions (see registers 0xC6 and 0xC7 of Register Maps). For the remote interrupt condition, the INTB pin
works in conjunction with the INTB_IN pin on the deserializer. This interrupt signal, when configured, will
propagate from the deserializer to the serializer.
1. On the Serializer, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. Deserializer INTB_IN pin is set LOW by some downstream device.
3. Serializer pulls INTB pin LOW. The signal is active LOW, so a LOW indicates an interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read HDCP_ISR register.
5. A read to HDCP_ISR will clear the interrupt at the Serializer, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt
source and clear the interrupt driving the Deserializer INTB_IN. This would be when the downstream device
releases the INTB_IN pin on the Deserializer. The system is now ready to return to step (2) at next falling
edge of INTB_IN.
8.3.9 Remote Interrupt Pin (REM_INTB)
REM_INTB will mirror the status of INTB_IN pin on the deserializer and does not need to be cleared. If the
serializer is not linked to the deserializer, REM_INTB will be high.
8.3.10 General-purpose I/O
8.3.10.1 GPIO[3:0] Configuration
In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (outputs) or back
channel (inputs) mode. GPIO modes may be configured from the registers. See Table 1 for GPIO enable and
configuration.
Description
GPIO3
GPIO2
GPIO1
GPIO0
Table 1. GPIO Enable and Configuration
Device
Serializer
Deserializer
Serializer
Deserializer
Serializer
Deserializer
Serializer
Deserializer
Forward Channel
0x0F[3:0] = 0x3
0x1F[3:0] = 0x5
0x0E[7:4] = 0x3
0x1E[7:4] = 0x5
0x0E[3:0] = 0x3
0x1E[3:0] = 0x5
0x0D[3:0] = 0x3
0x1D[3:0] = 0x5
Back Channel
0x0F[3:0] = 0x5
0x1F[3:0] = 0x3
0x0E[7:4] = 0x5
0x1E[7:4] = 0x3
0x0E[3:0] = 0x5
0x1E[3:0] = 0x3
0x0D[3:0] = 0x5
0x1D[3:0] = 0x3
8.3.10.2 Back Channel Configuration
The D_GPIO[3:0] pins can be configured to obtain different sampling rates depending on the mode as well as
back channel frequency. These different modes are controlled by a compatible deserializer. Consult the
appropriate deserializer datasheet for details on how to configure the back channel frequency. See Table 2 for
details about D_GPIOs in various modes.
Copyright © 2014, Texas Instruments Incorporated
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