DS90UH947-Q1 Datasheet, PDF (57/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

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ADD
(dec)
96
ADD
(hex)
0x60
Register Name
SPI_TIMING1
97
0x61 SPI_TIMING2
98
0x62 SPI_CONFIG
DS90UH947-Q1
SNLS455 – NOVEMBER 2014
Table 10. Serial Control Bus Registers (continued)
Bit(s)
7:4
3:0
7:4
3:0
7
6:3
2
1
0
Register
Type
RW
RW
RW
R
RW
R
RW
Default
(hex)
0x02
0x02
0x00
0x00
0x00
0x00
0x00
Function
Description
SPI_HOLD
SPI Data Hold from SPI clock: These bits set the minimum hold time
for SPI data following the SPI clock sampling edge. In addition, this
also sets the minimum active pulse width for the SPI output clock.
Hold = (SPI_HOLD + 1) * 40ns.
For example, default setting of 2 will result in 120ns data hold time.
SPI_SETUP
SPI Data Setup to SPI Clock: These bits set the minimum setup time
for SPI data to the SPI clock active edge. In addition, this also sets the
minimum inactive width for the SPI output clock.
Setup = (SPI_SETUP + 1) * 40ns.
For example, default setting of 2 will result in 120ns data setup time.
Reserved.
SPI_SS_SETUP SPI Slave Select Setup: This field controls the delay from assertion of
the Slave Select low to initial data timing. Delays are in units of 40ns.
Delay = (SPI_SS_SETUP + 1) * 40ns.
SPI_MSTR_OVE SPI Master Overflow Detection: This flag is set if the SPI Master
R
detects an overflow condition. This occurs if the SPI Master is unable
to regenerate the remote SPI data at a fast enough rate to keep up
with data arriving from the remote Deserializer. If this condition occurs,
it suggests the SPI_SETUP and SPI_HOLD times should be set to
smaller values. This flag is cleared by setting the SPI_CLR_OVER bit
in this register.
Reserved.
SPI_CLR_OVER Clear SPI Master Overflow Flag: Setting this bit to 1 will clear the SPI
Master Overflow Detection flag (SPI_MSTR_OVER). This bit is not
self-clearing and must be set back to 0.
SPI_CPHA
SPI Clock Phase setting: Determines which phase of the SPI clock is
used for sampling data.
0: Data sampled on leading (first) clock edge.
1: Data sampled on trailing (second) clock edge.
This bit is read-only, with a value of 0. The DS90UH947-Q1 does not
support CPHA of 1.
SPI_CPOL
SPI Clock Polarity setting: Determines the base (inactive) value of the
SPI clock.
0: base value of the clock is 0.
1: base value of the clock is 1.
This bit affects both capture and propagation of SPI signals.
Copyright © 2014, Texas Instruments Incorporated
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