DS90UH947-Q1 Datasheet, PDF (74/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

DS90UH947-Q1
SNLS455 – NOVEMBER 2014
Typical Applications (continued)
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Graphics
Processor
FPD-Link
(OpenLDI)
CLK+/-
D0+/-
D1+/-
D2+/-
D3+/-
D4+/-
D5+/-
D6+/-
D7+/-
VDDIO
1.8V
1.8V 1.1V
DOUT0+
DOUT0-
DOUT1+
DOUT1-
DS90UH947-Q1
Serializer
FPD-Link III
2 lanes @3Gbps / per
Lane
1.2V 3.3V
VDDIO
1.8V or 3.3V
RIN0+
RIN0-
RIN1+
RIN1-
DS90UH948-Q1
Deserializer
I2C
IDx
D_GPIO
(SPI)
I2C
IDx
D_GPIO
(SPI)
FPD-Link
(OpenLDI)
CLK+/-
D0+/-
D1+/-
D2+/-
D3+/-
CLK2+/-
D4+/-
D5+/-
D6+/-
D7+/-
HDCP ± High-Bandwidth Digital Content Protection
Figure 37. Typical System Diagram
LVDS
Display
1080p60
or Graphic
Processor
9.2.1 Design Requirements
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.
External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 38.
Table 11. Design Parameters
DESIGN PARAMETER
VDDIO
AC Coupling Capacitor for DOUT0± and DOUT1± with 92x
deserializers
AC Coupling Capacitor for DOUT0± and DOUT1± with 94x
deserializers
EXAMPLE VALUE
1.8V
100nF
33nF
For applications utilizing single-ended 50Ω coaxial cable, the unused data pins (DOUT0-, DOUT1-) should utilize
a 15nF capacitor and should be terminated with a 50Ω resistor.
SER
D_OUT+
D_OUT-
R_IN+
R_IN-
DES
Figure 38. AC-Coupled Connection (STP)
SER
D_OUT+
R_IN+
DES
D_OUT-
503
503
R_IN-
Figure 39. AC-Coupled Connection (Coaxial)
For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics.
74
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