DS90UH947-Q1 Datasheet, PDF (18/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

DS90UH947-Q1
SNLS455 – NOVEMBER 2014
Feature Description (continued)
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CLK +/-
(Differential)
D0 +/-
Previous cycle
GO2
RO7
Current cycle
RO6
RO5
RO4
RO3
RO2
D1 +/-
D2 +/-
BO3
BO2
GO7
GO6
GO5
GO4
GO3
DE
VS
HS
BO7
BO6
BO5
BO4
D3 +/-
--
BO1
BO0
GO1
GO0
RO1
RO0
D4~D7 +/-
Figure 16. 24-bit Color Single Pixel Mapping: LSBs on D3 (SPWG Mapping)
8.3.5 Video Control Signals
The video control signal bits embedded in the high-speed FPD-Link LVDS are subject to certain limitations
relative to the video pixel clock period (PCLK). By default, the DS90UH947-Q1 applies a minimum pulse width
filter on these signals to help eliminate spurious transitions.
Normal Mode Control Signals (VS, HS, DE) have the following restrictions:
• Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 10. HS can have at most two transitions per 130 PCLKs.
• Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum
pulse width is 130 PCLKs.
• Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 10. DE can have at most two transitions per 130 PCLKs.
8.3.6 Power Down (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an
external device, or through V_DDIO, where V_DDIO = 1.71V to 1.89V. To save power, disable the link when the
display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before all power supplies have
reached final levels. When PDB is driven low, ensure that the pin is driven to 0V for at least 3ms before releasing
or driving high. In the case where PDB is pulled up to V_DDIO directly, a 10kΩ pull-up resistor and a >10µF
capacitor to ground are required (See Power Up Requirements And PDB Pin).
Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time,
PDB must be held low for a minimum of 3ms before going high again.
8.3.7 Serial Link Fault Detect
The DS90UH947-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the
Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 10). The DS90UH947-Q1 will
detect any of the following conditions:
1. Cable open
2. “+” to “-” short
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