DS90UH947-Q1 Datasheet, PDF (5/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

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DS90UH947-Q1
SNLS455 – NOVEMBER 2014
Pin Functions (continued)
Pin Name
GPIO0
GPIO1
GPIO2
Pin #
14
15
38
I/O, Type
IO, LVCMOS
IO, LVCMOS
IO, LVCMOS
GPIO3
39
IO, LVCMOS
Register-Only GPIO Pins
GPIO5_REG
37
IO, LVCMOS
GPIO6_REG
36
IO, LVCMOS
GPIO7_REG
34
IO, LVCMOS
GPIO8_REG
35
IO, LVCMOS
Slave Mode Local I2S Channel Pins
I2S_WC
34
I, LVCMOS
I2S_CLK
35
I, LVCMOS
I2S_DA
36
I, LVCMOS
I2S_DB
37
I, LVCMOS
I2S_DC
38
I, LVCMOS
I2S_DD
39
I, LVCMOS
Power & Ground Pins
VDD18
24
Power
62
VDDOA11
50
Power
64
VDDA11
12
Power
VDDHS11
21
Power
28
VDDL11
9
Power
42
VDDOP11
61
Power
VDDP11
17
Power
VDDS11
25
Power
VDDIO
16
Power
33
GND
Thermal
Pad
Other Pins
RES0
29
RES2
40
RES3
41
RES1
30
NC
11
Description
General Purpose Input/Output 0
General Purpose Input/Output 1
General Purpose Input/Output 2
Shared with I2S_DC
General Purpose Input/Output 3
Shared with I2S_DD
General Purpose Input/Output 5
Local register control only. Shared with I2S_DB
General Purpose Input/Output 6
Local register control only. Shared with I2S_DA
General Purpose Input/Output 7
Local register control only. Shared with I2S_WC
General Purpose Input/Output 8
Local register control only. Shared with I2S_CLK
Slave Mode I2S Word Clock Input. Shared with GPIO7_REG
Slave Mode I2S Clock Input. Shared with GPIO8_REG
Slave Mode I2S Data Input. Shared with GPIO6_REG
Slave Mode I2S Data Input. Shared with GPIO5_REG
Slave Mode I2S Data Input. Shared with GPIO2
Slave Mode I2S Data Input. Shared with GPIO3
1.8V (±5%) supply. Refer to Figure 35 or Figure 36.
1.1V (±5%) supply. Refer to Figure 35 or Figure 36.
1.1V (±5%) supply. Refer to Figure 35 or Figure 36.
1.1V (±5%) supply. Refer to Figure 35 or Figure 36.
1.1V (±5%) supply. Refer to Figure 35 or Figure 36.
1.1V (±5%) supply. Refer to Figure 35 or Figure 36.
1.1V (±5%) supply. Refer to Figure 35 or Figure 36.
1.1V (±5%) supply. Refer to Figure 35 or Figure 36.
1.8V (±5%) LVCMOS I/O Power. Refer to Figure 35 or Figure 36.
Ground.
Reserved. Tie to GND.
Reserved. Connect with 50Ω to GND.
No connect. Leave floating Do not connect to VDD or GND.
Copyright © 2014, Texas Instruments Incorporated
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