DS90UH947-Q1 Datasheet, PDF (24/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

DS90UH947-Q1
SNLS455 – NOVEMBER 2014
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For both Reverse Channel SPI writes and reads, the SPI_SS signal should be deasserted for at least one back
channel frame period.
Table 4. SPI SS Deassertion Requirement
Back Channel Frequency
5 Mbps
10 Mbps
20 Mbps
Deassertion Requirement
7.5 µs
3.75 µs
1.875 µs
8.3.12 Backward Compatibility
This FPD-Link III serializer is backward compatible to the DS90UH926Q-Q1 and DS90UH928Q-Q1 for OpenLDI
clock frequencies ranging from 25MHz to 85MHz. Backward compatibility does not need to be enabled. When
paired with a backward compatible device, the serializer will auto-detect to 1-lane FPD-Link III on the primary
channel (DOUT0±).
8.3.13 Audio Modes
8.3.13.1 I2S Audio Interface
The DS90UH947-Q1 serializer features six I2S input pins that, when paired with a compatible deserializer,
supports 7.1 High-Definition (HD) Surround Sound audio applications. The bit clock (I2S_CLK) supports
frequencies between 1MHz and the lesser of CLK/2 or 13MHz. Four I2S data inputs transport two channels of
I2S-formatted digital audio each, with each channel delineated by the word select (I2S_WC) input. Refer to
Figure 21 and Figure 22 for I2S connection diagram and timing information.
I2S
Transmitter
Bit Clock
Word Select
Data
4
Serializer
I2S_CLK
I2S_WC
I2S_Dx
Figure 21. I2S Connection Diagram
I2S_WC
I2S_CLK
I2S_Dx
MSB
LSB MSB
LSB
Figure 22. I2S Frame Timing Diagram
Table 5 covers several common I2S sample rates:
Sample Rate (kHz)
32
44.1
48
96
192
32
44.1
Table 5. Audio Interface Frequencies
I2S Data Word Size (bits)
16
16
16
16
16
24
24
I2S CLK (MHz)
1.024
1.411
1.536
3.072
6.144
1.536
2.117
24
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