DS90UH947-Q1 Datasheet, PDF (35/87 Pages) Texas Instruments – 1080p OpenLDI to FPD-Link III Serializer with HDCP

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DS90UH947-Q1
SNLS455 – NOVEMBER 2014
Programming (continued)
Table 9. Serial Control Bus Addresses For IDx (continued)
#
Ratio
V_R2 / V_DD18
6
0.673
7
0.789
8
1
Ideal V_R2
(V)
1.212
1.421
1.8
Suggested Resistor Suggested Resistor
R1 kΩ (1% tol)
R2 kΩ (1% tol)
66.5
137
21.5
80.6
40.2
OPEN
7-Bit Address
0x16
0x18
0x1A
8-Bit Address
0x2C
0x30
0x34
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See
Figure 32
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 32. Start And Stop Conditions
To communicate with an I2C slave, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 25 and a WRITE is shown in Figure 26.
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
S
Slave Address
a
AA
21
A
0
1
c
k
Data
a
c
k
P
Figure 33. Serial Control Bus — Read
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
Data
a
c
k
P
Figure 34. Serial Control Bus — Write
The I2C Master located at the serializer must support I2C clock stretching. For more information on I2C interface
requirements and throughput considerations, please refer to TI Application Note SNLA131.
8.5.2 Multi-Master Arbitration Support
The Bidirectional Control Channel in the FPD-Link III devices implements I2C compatible bus arbitration in the
proxy I2C master implementation. When sending a data bit, each I2C master senses the value on the SDA line.
If the master is sending a logic 1 but senses a logic 0, the master has lost arbitration. It will stop driving SDA,
retrying the transaction when the bus becomes idle. Thus, multiple I2C masters may be implemented in the
system.
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