RIVA128ZX Datasheet, PDF (83/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
Byte offsets 0x63 - 0x60
0x63
0x62
0x61
0x60
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Power Management Capabilities Register (0x63 - 0x60)
Bits
31:19
18:16
15:8
7:0
Function
Reserved
VERSION indicates that RIVA128ZX is compliant with Revision 1.0 of the PCI
Power Management Interface Specification.
NEXT_PTR indicates the offset for the next item in the capability list. If the
power-on reset configuration Host Interface bit indicates PCI then NEXT_PTR
will be null (0x00), indicating there are no further items. If the power-on reset
configuration indicates AGP then NEXT_PTR will indicate the next item’s off-
set (the AGP capability, 0x44).
A value of ‘1’ read back from CAP_ID indicates this is the Power Management
Register.
RWI
R-0
R-1
R -X
R-1
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