RIVA128ZX Datasheet, PDF (40/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 40. SDRAM/SGRAM read to precharge, read latency of three
FBCLKx
Command
FBA[10:0]
FBD[63:0]
tRP
read precharge nop
bank, bank(s)
col n
nop active
bank,
row
data n
NOTE
1 FBDQM is active (low)
Figure 41. SDRAM/SGRAM Write to Precharge
FBCLKx
FBDQM#
Command
write
nop
nop
precharge
FBA[10:0] _{bank, col n}
tWR
FBD[63:0] _{write data n write data}
n+1
bank(s)
tRP
nop
nop
active
row
Figure 42. SDRAM/SGRAM Active to Read or Write
FBCLKx
Command
active
nop
nop
tRCD
Table 12. SDRAM/SGRAM timing parameters
Symbol
tCS
tCH
tMTC
tRAS
tRC
tRCD
Parameter
FBCSx, FBRAS#, FBCAS#, FBWE#,
FBDQM setup time
FBCSx, FBRAS#, FBCAS#, FBWE#,
FBDQM hold time
Load Mode register command to command
Active to Precharge command period
Active to Active command period
Active to Read or Write delay
Min.
3
1
2
7
10
3
40/85
read or write
Max.
Unit
ns
ns
tCK
tCK
tCK
tCK
Notes