RIVA128ZX Datasheet, PDF (38/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Symbol
Parameter
tDH
Write data hold time
tOH
Read data hold time
tAC
Read data access time
tLZ
Data out low impedance time
Min.
-10
-12
1
1
3
3
9
9
0
0
Max.
Unit
-10
-12
-
ns
-
ns
-
ns
-
ns
Figure 34. SDRAM/SGRAM random read accesses within a page, read latency of two¹
Notes
FBCLKx
Command
FBA[10:0]
FBD[63:0]
read
read
read
read
nop
bank, col n bank, col a bank, col x bank, col m
data n
data a
data x
nop
data m
NOTE
1 Covers either successive reads to the active row in a given bank, or to the active rows in different banks. DQMs are all
active (LOW).
Figure 35. SDRAM/SGRAM random read accesses within a page, read latency of three¹
FBCLKx
Command
FBA[10:0]
FBD[63:0]
read
read
read
read
nop
nop
nop
bank, col n bank, col a bank, col x bank, col m
data n data a data x data m
NOTE
1 Covers either successive reads to the active row in a given bank, or to the active rows in different banks. FBDQM is all
active (LOW).
Figure 36. SDRAM/SGRAM read to write, read latency of three
FBCLKx
TDDQM
Command
read
nop
nop
nop
write
FBA[10:0]
bank, col n
bank, col b
FBD[63:0]
tHZ
read data n
tDS
write data b
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