RIVA128ZX Datasheet, PDF (39/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

128-BIT 3D MULTIMEDIA ACCELERATOR
Table 11. SDRAM/SGRAM I/O timing parameters
Symbol
tHZ
tDS
Parameter
Data out high impedance time
Write data setup time
Min.
4
4
Figure 37. SDRAM/SGRAM random write cycles within a page
Max.
10
RIVA128ZX
Unit
Notes
ns
ns
FBCLKx
Command
FBA[10:0]
FBD[63:0]
write
bank, col n
data n
write
bank, col a
data a
write
bank, col x
data x
write
bank, col m
data m
NOTE
1 Covers either successive writes to the active row in a given bank or to the active rows in different banks. FBDQM is active
(low).
Figure 38. SDRAM/SGRAM write to read cycle
FBCLKx
Command
write
nop
read
nop
nop
nop
bank,
bank,
FBA[10:0]
col n
col b
FBD[63:0]
write
data n
write
data n
read
data b
NOTE
1 A read latency of 2 is shown for illustration
Figure 39. SDRAM/SGRAM read to precharge, read latency of two
tRP
FBCLKx
Command
read precharge nop
nop active
FBA[10:0]
FBD[63:0]
bank, col n bank(s)
data n
bank,row
NOTE
1 FBDQM is active (low)
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