RIVA128ZX Datasheet, PDF (55/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
10 POWER-ON RESET CONFIGURATION
The RIVA128ZX latches its configuration on the
trailing edge of RST# and holds its system bus in-
terface in a high impedance state until this time. To
accomplish this, pull-up or pull-down resistors are
connected to the FBA[9:0] pins as appropriate.
Since there are no internal pull-up or pull-down re-
sistors and the address bus should be floating dur-
ing reset, a resistor value of up to 47KΩ, but no
less than 10KΩ, should be sufficient.
The power-on reset configuration seen by the chip
may be overwritten. The external FBA[9:0] config-
uration is stored in latches. An additional writable
register, containing all of the configuration bits
Power-on reset FBA[9:0] bit assignments
plus an additional STRAP_OVERWRITE bit (reg-
ister bit [11]), exists in parallel with the latches to
allow the host to overwrite the external value. Writ-
ing to address BOOT_0 (0x00101000) writes into
this register.
The STRAP_OVERWRITE bit controls whether
the latches or the parallel writable register are se-
lected. When STRAP_OVERWRITE is set to 0,
the latched FBA[9:0] configuration is selected.
When set to 1, the chip uses the register value.
Reading from address BOOT_0 reads either the
configuration latches or the parallel register de-
pending on the STRAP_OVERWRITE setting.
9
AGP
Mode
8
7
TV Mode
6
5
4
Crystal Host RAM
Interface Width
3
ACPI
Sup-
ported
2
RAM
Type
1
Sub-
Vendor
0
Bus
Speed
[9]
[8:7]
[6]
[5]
[4]
[3]
AGP Mode. This bit selects whether the AGP bus 1X or 2X mode is enabled.
0 = AGP 2X mode enabled
1 = AGP 1X mode enabled
TV Mode. These bits select the timing format when TV mode is enabled.
00 = Reserved
01 = NTSC
10 = PAL
11 = TV mode disabled
Crystal Frequency. This bit should match the frequency of the crystal or reference clock connect-
ed to XTALOUT and XTALIN.
0 = 13.500MHz (used where TV output may be enabled)
1 = 14.31818MHz
Host Interface
0 = PCI
1 = AGP
RAM Width
0 = 64-bit framebuffer data bus width (the upper 64-bit data bus and byte selects are tri-state)
1 = 128-bit framebuffer data bus width
Although a 10KΩ resistor is used to strap the default state of this bit in RIVA 128 and RIVA128ZX
reference designs, it is ignored by the video BIOS which auto-detects the memory type and con-
figures the RIVA128ZX appropriately.
APCI Supported
0 = ACPI registers not supported. This provides compatibility with the PCI register configuration
as implemented by RIVA 128. The RIVA128ZX will be identified by DEVICE_ID_CHIP = 0x18 at
PCI Configuration offset 0x0.
1 = ACPI registers supported. Power management registers supported in PCI configuration
space. The RIVA128ZX will be identified by DEVICE_ID_CHIP = 0x19 at PCI Configuration offset
0x0.
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