RIVA128ZX Datasheet, PDF (54/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Table 18. ROM interface timing parameters
Symbol
Parameter
Min.
tBRCS
tBRCA
tBRV
tBRH
tBAS
tBAH
tBOS
tBOH
tBWS
tBWL
tBDBZ
tBDS
tBDH
tBDZ
tBWDH
tBWDS
ROMCS# active pulse width
ROMCS# precharge time
Read valid to ROMCS# active
Read hold from ROMCS# inactive
Address setup to ROMCS# active
Address hold from ROMCS# inactive
OE# low from ROMCS# active
OE# low to ROMCS# inactive
WE# low from ROMCS# active
WE# low time
Data bus high-z to ROMCS# active
Data setup to ROMCS# inactive
Data hold from ROMCS# inactive
Data high-z from ROMCS# inactive
Write data hold from ROMCS# inactive
ROM write data setup to ROMCS# active
20TMCLK-5
TMCLK-5
TMCLK-5
TMCLK-5
TMCLK-5
TMCLK-5
TMCLK-5
10
0
0.5TMCLK-5
TMCLK-5
NOTE
1
2
3
TMCLK is the period of the internal memory clock.
This parameter is programmable in the range 0 - 3 MCLK cycles
This parameter is programmable in the range 0 - 15 MCLK cycles
Max.
TMCLK-5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2
3
2
3
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