RIVA128ZX Datasheet, PDF (17/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 5. Basic AGP pipeline concept
RIVA128ZX
Bus Idle
Pipelined
data
transfer
Data-1
Data-2
Data-3
Intervene
cycles
A1 A2
A3
Pipelined AGP requests
A Data
PCI transaction
Pipeline operation
Memory access pipelining provides the main per-
formance enhancement of AGP over PCI. AGP
pipelined bus transactions share most of the PCI
signal set, and are interleaved with PCI transac-
tions on the bus.
The RIVA128ZX supports AGP pipelined reads
with a 4-deep queue of outstanding read requests.
Pipelined reads are primarily used by the
RIVA128ZX for cache filling, the cache size being
optimized for AGP bursts. Depending on the AGP
bridge, a bandwidth of up to 248MByte/s is achiev-
able for 128-byte pipelined reads. This compares
with around 100MByte/s for 128-byte 33MHz PCI
reads. Another feature of AGP is that for smaller
sized reads the bandwidth is not significantly re-
duced. Whereas 16-byte reads on PCI transfer at
around 33MByte/s, on AGP around 175MByte/s is
achievable. The RIVA128ZX actually requests
reads greater than 64 bytes in multiples of 32-byte
transactions.
The pipe depth can be maintained by the AGP bus
master (RIVA128ZX) intervening in a pipelined
transfer to insert new requests between data re-
plies. This bus sequencing is illustrated in Figure
5.
When the bus is in an idle condition, the pipe can
be started by inserting one or more AGP access
requests consecutively. Once the data reply to
those accesses starts, that stream can be broken
(or intervened) by the bus master (RIVA128ZX) in-
serting one or more additional AGP access re-
quests or inserting a PCI transaction. This inter-
vention is accomplished with the bus ownership
signals, PCIREQ# and PCIGNT#.
The RIVA128ZX implements both high and low
priority reads depending of the status of the ren-
dering engine. If the pipeline is likely to stall due to
system memory read latency, a high priority read
request is posted.
Address Transactions
The RIVA128ZX requests permission from the
bridge to use PCIAD[31:0] to initiate either an
AGP request or a PCI transaction by asserting
PCIREQ#. The arbiter grants permission by as-
serting PCIGNT# with AGPST[2:0] equal to ”111”
(referred to as START). When the RIVA128ZX re-
ceives START it must start the bus operation with-
in two clocks of the bus becoming available. For
example, when the bus is in an idle condition when
START is received, the RIVA128ZX must initiate
the bus transaction on the next clock and the one
following.
Figure 6 shows a single address being enqueued
by the RIVA128ZX. Sometime before clock 1, the
RIVA128ZX asserts PCIREQ# to gain permission
to use PCIAD[31:0]. The arbiter grants permission
by indicating START on clock 2. A new request
(address, command and length) are enqueued on
each clock in which AGPPIPE# is asserted. The
address of the request to be enqueued is present-
ed on PCIAD[31:3], the length on PCIAD[2:0] and
the command on PCICBE[3:0]#. In Figure 6 only
a single address is enqueued since AGPPIPE# is
just asserted for a single clock. The RIVA128ZX
indicates that the current address is the last it in-
tends to enqueue when AGPPIPE# is asserted
and PCIREQ# is deasserted (occurring on clock
3). Once the arbiter detects the assertion of AGP-
PIPE# or PCIFRAME# it deasserts PCIGNT# on
clock 4.
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