RIVA128ZX Datasheet, PDF (70/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x07 - 0x04
0x07
0x06
0x05
0x04
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Device Status Register (0x07 - 0x06)
Bits
31
30
29
28
27
26:25
24:22
21
20
19:16
Function
Reserved
SERR_SIGNALLED is set whenever the RIVA128ZX asserts SERR#.
RECEIVED_MASTER indicates that a master device’s transaction (except for
Special Cycle) was terminated with a master-abort. This bit is clearable (=1).
0=No abort
1=Master aborted
RECEIVED_TARGET indicates that a master device’s transaction was termi-
nated with a target-abort. This bit is clearable (=1).
0=No abort
1=Master received target aborted
Reserved
The DEVSEL_TIMING bits indicate the timing of DEVSEL#. These bits indi-
cate the slowest time that the RIVA128ZX asserts DEVSEL# for any bus
command except Configuration Read and Configuration Write. The
RIVA128ZX responds with medium DEVSEL# for VGA, memory and I/O
accesses. For accesses to the 16MByte memory ranges described by the
BARs, the chip responds with fast decode (no wait states).
00=fast
01=medium
Reserved
66MHZ indicates that the RIVA128ZX is capable of 66MHz operation. This bit
reflects the latched state of the 66MHz/33MHz strap option.
CAP_LIST indicates that there is a linked list of registers containing informa-
tion about new capabilities not available within the original PCI configuration
structure. This bit indicates that the (byte) Capability Pointer Register located
at 0x34 points to the start of this linked list.
The value of CAP_LIST depends on the RIVA128ZX power-on reset configu-
ration Host Interface and ACPI Supported settings:
0 = Host Interface is PCI and ACPI not supported
1= Host interface is AGP or ACPI supported
Reserved
RWI
R-0
RW0
RW0
RW0
R-0
R-1
R-0
R-1
R -X
R-0
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