RIVA128ZX Datasheet, PDF (77/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
Byte offsets 0x33 - 0x30
0x33
0x32
0x31
0x30
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Expansion ROM Base Address Register (0x33 - 0x30)
Bits
31:22
21:11
10:1
0
Function
The ROM_BASE_ADDR bits contain the base address of the Expansion
ROM. The bits correspond to the upper bits of the Expansion ROM base
address. This decode permits the PCI boot manager to place the expansion
ROM on a 4MByte boundary. RIVA128ZX currently maps a 64KByte BIOS
into the bottom of this 4MByte range. Typically the first 32K of this ROM con-
tains the VGA BIOS code as well as the PCI BIOS Expansion ROM Header
and Data Structure.
ROM_BASE_RESERVED contain the lower bits of the base address of the
Expansion ROM. These bits are hardwired to 0, forcing a 4MByte boundary.
Reserved
The ROM_DECODE bit indicates whether or not the RIVA128ZX accepts
accesses to its expansion ROM. When the bit is set, address decoding is
enabled using the parameters in the other part of the base register. The
MEMORY_SPACE bit (PCI Configuration Register 0x04, page 70) has prece-
dence over the ROM_DECODE bit. RIVA128ZX will respond to accesses to
its expansion ROM only if both the MEMORY_SPACE bit and the
ROM_DECODE bit are set to 1.
0=Expansion ROM address space is disabled
1=Expansion ROM address decoding is enabled
RWI
RWX
R-0
R-0
RW0
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