RIVA128ZX Datasheet, PDF (7/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
Signal
PCIGNT#
PCIINTA#
I/O Description
I Grant. This signal indicates to the RIVA128ZX that access to the bus has been granted
and it can now become bus master.
When connected to AGP additional information is provided on AGPST[2:0] indicating that
the master is the recipient of previously requested read data (high or low priority), it is to
provide write data (high or low priority), for a previously enqueued write command or has
been given permission to start a bus transaction (AGP or PCI).
O Interrupt request line. This open drain output is asserted and deasserted asynchronously
to PCICLK.
2.3 FRAMEBUFFER INTERFACE
Signal
FBD[127:0]
FBA[10:0]
FBRAS#
FBCAS#
FBCS[1:0]#
FBWE#
FBDQM[15:0]
FBCLK0,
FBCLK1,
FBCLK2
FBCLKFB
FBCKE
I/O Description
I/O The 128-bit memory data bus.
FBD[31:0] are also used to access up to 64KBytes of 8-bit ROM or Flash ROM, using
FBD[15:0] as address ROMA[15:0], FBD[31:24] as ROMD[7:0], FBD[17] as ROMWE#
and FBD[16] as ROMOE#.
O Memory Address bus. Configur ation strapping options are also decoded on these signals
during PCIRST# as described in Section 10, page 55.
O Memory Row Address Strobe for all memory devices.
O Memory Column Address Strobe for all memory devices.
O Memory Chip Select strobes. For SDRAM the FBCS[1] pin provides the memory’s inter-
nal bank select bit (BA/A11).
O Memory Write Enable strobe for all memory devices.
O Memory Data/Output Enable strobes.
O Memory Clock signals. Separate clock signals FBCLK0 and FBCLK1 are provided for
each bank of memory for reduced clock skew and loading. Details of recommended mem-
ory clock layout are given in Section 6.4, page 37.
I Framebuffer clock feedback. FBCLK2 is fed back to FBCLKFB.
O Framebuffer memory clock enable signal.
2.4 VIDEO PORT
Signal
MP_AD[7:0]
MPCLK
MPDTACK#
MPFRAME#
MPSTOP#
I/O Description
I/O Media Port 8-bit multiplexed address and data bus or ITU-R-656 video data bus when in
656 mode.
I 40MHz Media Port system clock or pixel clock when in 656 mode.
I Media Port data transfer acknowledgment signal.
O Initiates Media Port transfers when active, terminates transfers when inactive.
I Media Port control signal used by the slave to terminate transfers.
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