RIVA128ZX Datasheet, PDF (72/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x0B - 0x08
0x0B
0x0A
0x09
0x08
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Class Code Register (0x0B - 0x09)
Bits Function
31:8 The CLASS_CODE bits identify the generic function of the device and (in
some cases) a specific register-level programming interface. The register is
broken into three byte-size fields. The upper byte (at offset 0x0B) is a base
class code which broadly classifies the type of function the device performs.
The middle-byte (at offset 0x0A) is a sub-class code which identifies more
specifically the function of the device. The lower byte (at offset 0x09) identifies
a specific register-level programming interface (if any) so that device indepen-
dent software can interact with the device.
The VGA function responds as a VGA compatible controller.
0x030000=VGA compatible controller
Revision Identification Register (0x08)
Bits Function
7:0
The REVISION_ID bits specify a device specific revision identifier. The value
is chosen by the vendor. This field should be vie wed as a vendor defined
extension to the DEVICE_ID.
0x01=Revision B
RWI
R -X
RWI
R-X
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