RIVA128ZX Datasheet, PDF (78/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x37 - 0x34
0x37
0x36
0x35
0x34
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Capabilities Pointer Register (0x37 - 0x34)
Bits Function
31:8 Reserved
7:0
This field contains a byte offset into this PCI configuration space containing
the first item in the capabilities list. The offset returned depends on the
RIVA128ZX power-on reset configuration Host Interface and ACPI Supported
settings:
CAP_PTR = 0x0 if Host Interface is PCI and APCI not supported
CAP_PTR = 0x44 if Host Interface is AGP and APCI not supported
CAP_PTR = 0x60 if APCI supported
RWI
R-0
R -X
Byte offsets 0x3B - 0x38
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x00000000
Reserved (0x3B - 0x38)
Bits Function
31:0 These bits are reserved and hardwired (read-only) to 0.
RWI
R-0
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