RIVA128ZX Datasheet, PDF (74/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x13 - 0x10
0x13
0x12
0x11
0x10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Base Memory Address Register (0x13 - 0x10)
Bits
31:24
23:4
3
2:1
0
Function
The BASE_ADDRESS bits contain the most significant bits of the base
address of the device. This indicates that the RIVA128ZX requires a 16MByte
block of contiguous memory beginning on a 16MByte boundary. This memory
range contains memory-mapped registers and FIFOs and should not be set
as part of a PentiumPro™’s write combining range.
The BASE_RESERVED bits form the least significant bits of the base address
and are hardwired to 0.
The PREFETCHABLE bit indicates that there are no side effects on reads,
that the device returns all bytes on reads regardless of the byte enables, and
that host bridges can merge processor writes into this range without causing
errors.
The ADDRESS_TYPE bits contain the type (width) of the Base Address.
0=32-bit
The SPACE_TYPE bit indicates whether the register maps into Memory or I/O
space.
0=Memory space
RWI
RW0
R-0
R-1
R-0
R-0
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