RIVA128ZX Datasheet, PDF (20/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 10. 2X Basic write no delay
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7
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9
PCICLK
PCIAD[31:0]
W1 +1 +2 +3 +4 +5 +6 +7
PCICBE#
BE BE BE BE BE BE BE BE
AGPADSTBx
PCIIRDY#
PCITRDY#
PCIREQ#
PCIGNT#
AGPST[2:0] xx xxx xxx 01x xxx xxx xxx xxx xxx
Figure 10 is a basic write transaction that transfers data at the 2X rate. There is no difference in the control
signals from AGP 1x mode - only more data is moved. The normal control signals determine when data is
valid.
Figure 11. QuadWord writes back to back - no delays
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2
3
4
5
6
7
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9
PCICLK
PCIAD[31:0]
W3 +1 W4 +1 W5 +1 W6 +1
W7 +1 W8 +1
PCICBE#
BE BE BE BE BE BE BE BE
BE BE BE BE
AGPADSTBx
PCIIRDY#
PCITRDY#
PCIGNT#
AGPST[2:0] xx 01x 01x 01x 01x xxx 01x 01x xxx x
Figure 11 illustrates multiple 8 byte write operations compared with the single transfer shown in Figure 10.
When the transactions are short, the arbiter is required to give grants on every clock or the AD bus will not
be totally utilized. In this example a new write is started on each rising clock edge except clock 7, because
the arbiter deasserted PCIGNT# on clock 6. Since a new transaction is started on each CLK, PCIIRDY#
is only deasserted on clock 7.
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