RIVA128ZX Datasheet, PDF (51/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
8.4 656 MASTER MODE
Table 15 shows the Video Port pin definition when
the RIVA128ZX is configured in ITU-R-656 Master
Mode. Before entering this mode, RIVA128ZX dis-
ables all Video Port devices so that the bus is tri-
stated. The RIVA128ZX will then enable the video
656 master device through the serial bus. In this
mode, the video device outputs the video data
continuously at the PIXCLK rate.
Table 15. 656 master mode pin definition
Normal Mode
MPCLK
MPAD[7:0]
MPFRAME#
MPDTACK#
MPSTOP#
656 Master Mode
PIXCLK
VID[7:0]
Not used
Not used
Not used
The 656 Master Mode assumes that VID[7:0] and
PIXCLK can be tri-stated when the slave is inac-
tive. If a slave cannot tri-state all its signals, an ex-
ternal tri-state buffer is needed.
Video data capture
Video Port pixel data is clocked into the port by the
external pixel clock and then passed to the
RIVA128ZX’s video capture FIFO.
Pixel data capture is controlled by the ITU-R-656
codes embedded in the data stream; each active
line beginning with SAV (start active video) and
ending with EAV (end active video).
In normal operation, when SAV = x00, capture of
video data begins, and when EAV = xx1, capture
of video data ends for that line. When VBI (Vertical
Blanking Interval) capture is active, these rules are
modified.
656 master mode timing specification
Figure 62. 656 Master Mode timing diagram
t5
PIXCLK
VID[7:0]
t3
t4
t3
t4
t3
t4
Table 16. ITU-R-656 Master Mode timing parameters
Symbol
t3
t4
t5
Parameter
VID[7:0] hold from PIXCLK high
VID[7:0] setup to PIXCLK high
PIXCLK cycle time
Min.
0
5
35
Max.
Unit
ns
ns
ns
NOTE
1 VACTIVE indicates that valid pixel data is being transmitted across the video port.
Table 17. YUV (YCbCr) byte ordering
1st byte
U[7:0]
Cb[7:0]
2nd byte
Y0[7:0]
Y0[7:0]
3rd byte
V[7:0]
Cr[7:0]
4th byte
Y1[7:0]
Y1[7:0]
5th (next
dword)
U[7:0]
Cb[7:0]
6th byte
Y0[7:0]
Y0[7:0]
Notes
7th byte
V[7:0]
Cr[7:0]
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