RIVA128ZX Datasheet, PDF (82/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x4F - 0x4C
0x4F
0x4E
0x4D
0x4C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AGP Command Register (0x4F - 0x4C = CAP_PTR + 8)
Bits
31:24
23:10
9
8
7:3
2:0
Function
This field is set to the minimum request depth of the target as reported in its
RQ field.
Reserved
SBA_ENABLE enables sideband addressing when set. The RIVA128ZX does
not implement sideband addressing.
AGP_ENABLE allows the RIVA128ZX to act as an AGP master and initiate
AGP operations. The target must be enabled before enabling the RIVA128ZX
0 = disabled
1 = AGP operations enabled
Reserved
The DATA_RATE field must be set to 0x01 to indicate 66MHz /1x transfer
mode or 0x02 for 133MHz/2x transfer mode. This value must also be set on
the target before being enabled. The initial value 0x00 indicates PCI opera-
tion.
RWI
RW-
R-0
R-0
RW0
R-0
R W 0x00
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