RIVA128ZX Datasheet, PDF (75/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
Byte offsets 0x17 - 0x14
0x17
0x16
0x15
0x14
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Base Memory Address Register (0x17 - 0x14)
Bits
31:24
23:4
3
2:1
0
Function
The BASE_ADDRESS bits contain the most significant bits of the base
address of the device. This indicates that the RIVA128ZX requires a 16MByte
block of contiguous memory beginning on a 16MByte boundary. This memory
range contains linear frame buffer access and may be set as part of a Pen-
tiumPro™’s write combining (wc) range.
The BASE_RESERVED bits form the least significant bits of the base address
and are hardwired to 0.
The PREFETCHABLE bit indicates that there are no side effects on reads,
that the device returns all bytes on reads regardless of the byte enables, and
that host bridges can merge processor writes into this range without causing
errors.
The ADDRESS_TYPE bits contain the type (width) of the Base Address.
0=32-bit
The SPACE_TYPE bit indicates whether the register maps into Memory or I/O
space.
0=Memory space
RWI
RW0
R-0
R-1
R-0
R-0
Byte offsets 0x2B - 0x18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x00000000
Base Address Registers (0x2B - 0x18)
Bits Function
31:0 These bits are hardwired (read-only) to 0.
RWI
R-0
75/85