RIVA128ZX Datasheet, PDF (36/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Table 9. Truth table of supported SGRAM commands
Command¹
FBCS0#, FBRAS# FBCAS# FBWE# FBDQM FBA[10:0]
FBCS1#
FBD[127:0] Notes
Command inhibit (NOP) H
x
x
x
xx
x
No operation (NOP)
L
H
H
H
xx
x
Active (select bank and
L
L
H
H
x FBA[10]=bank
x
activate row)
FBA[9:0]=row
Read (select bank and
L
H
L
H
x FBA[10]=bank
x
column and start read
FBA[9]=0
burst)
FBA[7:0]=col
Write (select bank and
L
H
L
L
x FBA[10]=bank valid data
column and start write
FBA[9]=0
burst)
FBA[7:0]=col
Precharge (deactivate
L
L
H
L
x FBA[10]=code
x
3
row in bank or banks)
Load mode register
L
L
L
L
x FBA[10:0] =
opcode
Write enable/output
enable
-
-
-
-
L-
active
2
Write inhibit/output
High-Z
-
-
-
-
H-
high-Z
2
NOTES
1
2
3
FBCKE is high and DSF is low for all supported commands.
Activates or deactivates FBD[127:0] during writes (zero clock delay) and reads (two-clock delay).
For FBA9 low, FBA10 determines which bank is precharged; for FBA9 high, all banks are precharged irrespective of the
state of FBA10.
SDRAM/SGRAM Initialization
SDRAM/SGRAMs must be powered-up and initialized in a predefined manner. The first SDRAM/SGRAM
command is registered on the first clock edge following PCIRST# inactive.
All internal SDRAM/SGRAM banks are precharged to bring the device(s) into the “all bank idle” state. The
SDRAM/SGRAM mode registers are then programmed and loaded to bring them into a defined state be-
fore performing any operational command.
SDRAM/SGRAM Mode register
The Mode register defines the mode of operation of the SDRAM/SGRAM. This includes burst length, burst
type, read latency and SDRAM/SGRAM operating mode. The Mode register is programmed via the Load
Mode register and retains its state until reprogrammed or power-down.
Mode register bits M[2:0] specify the burst length; for the RIVA128ZX SDRAM/SGRAM interface these bits
are set to zero, selecting a burst length of one. In this case FBA[7:0] select the unique column to be ac-
cessed and Mode register bit M[3] is ignored. Mode register bits M[6:4] specify the read latency; for the
RIVA128ZX SDRAM/SGRAM interface these bits are set to either 2 or 3, selecting a burst length of 2 or
3 respectively.
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