RIVA128ZX Datasheet, PDF (48/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 50. CPU read issue cycle - cannot be throttled by slave
MPCLK
MPFRAME#
MP_AD[7:0]
A0 A1/D
Figure 51. CPU read_receive cycle
MPCLK
MPFRAME#
MP_AD[7:0]
A0
D0
MPDTACK#
Figure 52. CPU read_receive cycle - throttled by slave
MPCLK
MPFRAME#
MP_AD[7:0]
A0
D0
MPDTACK#
Figure 53. CD write cycle - terminated by master
MPCLK
MPFRAME#
MP_AD[7:0]
A0
D0
D1
D2
D3
MPDTACK#
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