RIVA128ZX Datasheet, PDF (19/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
Figure 8. 2X Read data, no delay
1
2
PCICLK
PCIAD[31:0]
AGPADSTBx
AGPRBF#
PCITRDY#
PCIREQ#
PCIGNT#
AGPST[2:0] xxx 00x
3
4
5
6
7
R1 +1 +2 +3 +4 +5 +6 +7
xxx
xxx
xxx
xxx
xxx
Figure 8 shows 32 bytes being transferred during 4 clocks (compared with 16 bytes in AGP 1x mode). The
control signals are identical. The AGPAD_STBx signal has been added when data is transferred at 8
bytes per PCICLK period. AGPAD_STBx represents AGPAD_STB0 and AGPAD_STB1 and are used
by the 2X interface logic to indicate when valid data is present on the AD bus. The control logic (PCITRDY#
in this case) indicates when data can be used by the target.
Figure 9. 2X Back to back read data, no delay
1
2
3
4
5
6
7
8
9
PCICLK
PCIAD[31:0]
L6 +1 H4 +1 +L7 +1 H5 +1 L8 +1 H6 +1 L9 +1
AGPADSTBx
AGPRBF#
PCITRDY#
PCIGNT#
AGPST[2:0] xx 000 001 000 001 000 001 000 001 xx
Figure 9 shows back to back 8 byte read transactions. AGPST[2:0] are shown toggling between “000”and
“001” to illustrate that they are actually changing. However, they are not required to change between high
and low priority to do back to back transactions. In this diagram, PCITRDY# is asserted on each clock
since a new transaction starts on each clock.
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