RIVA128ZX Datasheet, PDF (2/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
TABLE OF CONTENTS
1 RIVA128ZX 300PBGA DEVICE PINOUT....................................................................................... 4
2 PIN DESCRIPTIONS ...................................................................................................................... 5
2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE ..................................................... 5
2.2 PCI 2.1 LOCAL BUS INTERFACE ........................................................................................ 5
2.3 FRAMEBUFFER INTERFACE .............................................................................................. 7
2.4 VIDEO PORT......................................................................................................................... 7
2.5 DEVICE ENABLE SIGNALS .................................................................................................. 8
2.6 DISPLAY INTERFACE .......................................................................................................... 8
2.7 VIDEO DAC AND PLL ANALOG SIGNALS .......................................................................... 8
2.8 POWER SUPPLY .................................................................................................................. 8
2.9 TEST...................................................................................................................................... 9
3 OVERVIEW OF THE RIVA128ZX .................................................................................................. 10
3.1 BALANCED PC SYSTEM...................................................................................................... 10
3.2 HOST INTERFACE ............................................................................................................... 10
3.3 2D ACCELERATION ............................................................................................................. 11
3.4 3D ENGINE ........................................................................................................................... 11
3.5 VIDEO PROCESSOR............................................................................................................ 11
3.6 VIDEO PORT......................................................................................................................... 12
3.7 DIRECT RGB OUTPUT TO LOW COST PAL/NTSC ENCODER ......................................... 12
3.8 SUPPORT FOR STANDARDS.............................................................................................. 12
3.9 RESOLUTIONS SUPPORTED.............................................................................................. 12
3.10 CUSTOMER EVALUATION KIT ............................................................................................ 13
3.11 TURNKEY MANUFACTURING PACKAGE ........................................................................... 13
4 ACCELERATED GRAPHICS PORT (AGP) INTERFACE ............................................................. 14
4.1 RIVA128ZX AGP INTERFACE .............................................................................................. 15
4.2 AGP BUS TRANSACTIONS.................................................................................................. 15
5 PCI 2.1 LOCAL BUS INTERFACE................................................................................................. 23
5.1 RIVA128ZX PCI INTERFACE ............................................................................................... 23
5.2 PCI TIMING SPECIFICATION ............................................................................................... 24
6 FRAMEBUFFER INTERFACE ....................................................................................................... 30
6.1 SDRAM INTERFACE ............................................................................................................ 31
6.2 SGRAM INTERFACE ............................................................................................................ 32
6.3 SDRAM/SGRAM ACCESSES AND COMMANDS ................................................................ 35
6.4 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS ................................................................ 37
6.5 FRAMEBUFFER INTERFACE TIMING SPECIFICATION .................................................... 37
7 VIDEO PLAYBACK ARCHITECTURE........................................................................................... 42
7.1 VIDEO SCALER PIPELINE ................................................................................................... 43
8 VIDEO PORT .................................................................................................................................. 45
8.1 VIDEO INTERFACE PORT FEATURES ............................................................................... 45
8.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC .............................. 46
8.3 TIMING DIAGRAMS .............................................................................................................. 47
8.4 656 MASTER MODE ............................................................................................................. 51
8.5 VBI HANDLING IN THE VIDEO PORT ................................................................................. 52
8.6 SCALING IN THE VIDEO PORT ........................................................................................... 52
9 BOOT ROM INTERFACE............................................................................................................... 53
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