RIVA128ZX Datasheet, PDF (30/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
6 FRAMEBUFFER INTERFACE
The RIVA128ZX framebuffer interface supports SDRAM and SGRAM memory. Using SDRAM it can be
configured with an 8MByte 64-bit data bus. With SGRAM it can be configured with a 2 or 4MByte 64-bit
data bus or a 4 or 8MByte 128-bit data bus. The memory configurations supported by RIVA128ZX are
shown in Table 7. All of the framebuffer signalling environment is 3.3V.
Table 7. RIVA128ZX memory configurations
2MByte
4MByte
8MByte
8Mbit
2 internal bank
SGRAM
2 devices
64-bit
4 devices
128-bit
2 banks of 4 devices
128-bit
16Mbit
2 internal bank
SGRAM
N/A
2 devices
64-bit
4 devices
128-bit
16Mbit
4 internal bank
SGRAM
N/A
2 devices
64-bit
4 devices
128-bit
16Mbit
1M x 16
SDRAM
N/A
N/A
4 devices
64-bit
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