RIVA128ZX Datasheet, PDF (16/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 3. Basic PCI transaction on AGP
1
PCICLK
2
3
PCIFRAME#
PCIAD[31:0]
address
PCICBE[3:0]#
bus cmd
PCIIRDY#
PCITRDY#
PCIDEVSEL#
PCIREQ#
PCIGNT#
AGPST[2:0] xxx
111
111
4
data_pci
BE[3:0]#
xxx
5
xxx
6
xxx
An example of a PCI transaction occurring between an AGP command cycle and return of data is shown
in Figure 4. This shows the smallest number of cycles during which an AGP request can be enqueued, a
PCI transaction performed and AGP read data returned.
Figure 4. PCI transaction occurring between AGP request and data
1
2
3
4
5
6
7
8
9
10
PCICLK
AGPPIPE#
PCIFRAME#
PCIAD[31:0]
A9
address data
D7
+1
PCICBE#
C9
pci_cmd BE
0000 000
PCIIRDY#
PCITRDY#
PCIDEVSEL#
PCIAGPRBF#
PCIREQ#
PCIGNT#
AGPST[2:0] ^{111 111}
xxx
111
111
xxx
xxx
00x
xxx
xxx
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