RIVA128ZX Datasheet, PDF (21/85 Pages) STMicroelectronics – 128-BIT 3D MULTIMEDIA ACCELERATOR

128-BIT 3D MULTIMEDIA ACCELERATOR
AGP timing specification
Figure 12. AGP clock specification
0.5VDD
PCICLK 0.4VDD
0.3VDD
0.6VDD
tCYC
0.2VDD
tHIGH
RIVA128ZX
tLOW
2V p-to-p
(minimum)
Table 1. AGP clock timing parameters
Symbol
tCYC
tHIGH
tLOW
Parameter
PCICLK period
PCICLK high time
PCICLK low time
PCICLK slew rate
Min.
15
6
6
1.5
Max.
30
4
Unit
ns
ns
ns
V/ns
NOTES
1 This rise and fall time is measured across the minimum peak-to-peak range as shown in Figure 12.
Figure 13. AGP timing diagram
Notes
1
AGPCLK
Output delay
Tri-state output
Input
tVAL
tVAL
tOFF
tON
data1
tSU
tH
data1
data2
data2
Table 2. AGP timing parameters
Symbol
tVAL
tON
tOFF
tSU
tH
Parameter
AGPCLK to signal valid delay (data and control
signals)
Float to active delay
Active to float delay
Input set up time to AGPCLK (data and control
signals)
Input hold time from AGPCLK
Min.
2
2
7
0
Max.
11
28
Unit
Notes
ns
ns
ns
ns
ns
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