SI5325C-C-GM Datasheet, PDF (90/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
6.13. I²C Serial Microprocessor Interface
When configured in I²C control mode (CMODE = L), the control interface to the device is a 2-wire bus for
bidirectional communication. The bus consists of a bidirectional serial data line (SDA) and a serial clock input
(SCL). Both lines must be connected to the positive supply via an external pull-up. In addition, an output interrupt
(INT) is provided with selectable active polarity (determined by INT_POL bit). Fast mode operation is supported for
transfer rates up to 400 kbps as specified in the I²C-Bus Specification standard. To provide bus address flexibility,
three pins (A[2:0]) are available to customize the LSBs of the device address. The complete bus address for the
device is as follows:
1 1 0 1 A[2] A[1] A[0] R/W.
Figure 32 shows the command format for both read and write access. Data is always sent MSB first. The timing
specifications and timing diagram for the I²C bus can be found in the I²C-Bus Specification standard (fast mode
operation) (See: http://www.standardics.nxp.com/literature/books/i2c/pdf/i2c.bus.specification.pdf).
The maximum I²C clock speed is 400 kHz.
S Slave Address 0 A
Byte
Address
A Data
Write Command
A Data
AP
S Slave Address 0 A
Byte
Address
A S Slave Address 1 A Data A Data A P
Read Command
–address auto incremented after each data read or write
(this can be two separate transactions)
From master to slave
A – Acknowledge (SDA LOW)
S ^{– START condition}
From slave to master
P ^{– STOP condition}
Figure 32. I²C Command Format
In Figure 33, the value 68 is seven bits. The sequence of the example is: Write register 00 with the value 0xAA;
then, read register 00. Note that 0 = Write = W, and 1 = Read = R.
S Slave Address
68
0 A Byte Address A
W
00
Write Command
Data
A
AA
S Slave Address 0 A Byte Address A S Slave Address 1 A Data
68
W
00
68
R
AA
Read Command
Figure 33. I²C Example
90
Rev. 1.2